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| ILX103A 3000-pixel CCD Linear Image Sensor (B/W) Description The ILX103A is a rectangular reduction type CCD linear image sensor designed for bar code POS hand scanner and optical measuring equipment use. A built-in timing generator and clock-drivers ensure single 5V power supply for easy use. Features * Number of effective pixels: 3000 pixels * Pixel size: 7m x 200m (7m pitch) * S/H output * Built-in timing generator and clock-drivers * Output amplifier gain switching function (2-level: switching gain ratio 1:4) * SIP small package * Clock frequency: 500kHz (Typ.), 100kHz (Min.), 1MHz (Max.) Absolute Maximum Ratings * Supply voltage VDD * Operating temperature * Storage temperature 16 pin SIP (Ceramic) Internal Structure 15 Readout gate pulse generator Shutter pulse generator 14 12 CCD analog shift register Readout gate Readout gate CCD analog shift register Driver Driver 13 6 1 Pin Configuration (Top View) 1 VDD 2 GND 3 Vout 4 Vgg 5 CLK 6 SWG 7 NC 8 NC 9 10 11 12 13 14 15 16 ROG SHUT GND GND VDD VDD NC T1 Output Amplifier 4 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- Vout 3 E98X48A91-PS SWG D24 D25 3000 1 2 CLK T1 S2999 S3000 D56 D54 D55 S1 S2 S3 VDD 6 -10 to +60 -30 to +80 V C C Timing generator 11 5 9 SHUT ROG 10 D65 GND VDD GND VDD GND Vgg ILX103A Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol VDD GND Vout Vgg CLK SWG NC NC ROG SHUT GND VDD T1 VDD GND NC Power supply GND Signal output Output circuit gate bias Clock pulse input Control (Output circuit amplification factor x4/x1) NC NC Readout gate pulse input Electrical shutter pulse input GND Power supply TEST (Connect to GND with 1000pF capacitor) Power supply GND NC Description Mode Description Output circuit gain High Low Pin 6 SWG VDD GND Recommended Voltage Item VDD Min. 4.5 Typ. 5.0 Max. 5.5 Unit V Input Pin Capacity Item Input capacity of CLK pin Input capacity of ROG pin Input capacity of SHUT pin Symbol CCLK CROG CSHUT Min. -- -- -- Typ. 10 10 10 Max. -- -- -- Unit pF pF pF -2- ILX103A Electro-optical Characteristics (Analog Characteristic) (Note 1) Ta = 25C, VDD = 5V, Clock frequency: 500kHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm), Output circuit gain low mode Item Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure 5V current consumption Total transfer efficiency Output impedance Offset level Symbol R1 R2 PRNU VSAT VDRK DSNU IL DR SE IVDD TTE ZO VOS Min. 52.5 -- -- 0.6 -- -- -- -- -- -- 92.0 -- -- Typ. 75 925 5.0 0.8 2.5 5.0 5.0 320 0.01 7.0 97.0 250 2.5 Max. 97.5 -- 10.0 -- 6.0 12.0 -- -- -- 17.0 -- -- -- Unit V/(lx * s) V/(lx * s) % V mV mV % -- lx * s mA % V Remarks Note 2 Note 3 Note 4 -- Note 5 Note 6 Note 7 Note 8 Note 9 -- -- -- Note 10 Note) 1. In accordance with the given electro-optical characteristics, the even black level is defined as the average value of D24, D25 to D53. 2. For the sensitivity test light is applied with a uniform intensity of illumination. 3. Light source: LED = 660nm 4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. PRNU = (VMAX - VMIN)/2 VAVE x 100 [%] 5. 6. 7. 8. 9. 10. The maximum output of the effective pixels is set to VMAX, the minimum output to VMIN and the average output to VAVE. Integration time is 10ms. The difference between the maximum and average values and the difference between the minimum and average values of the dark output voltage is calculated. The larger value is defined as dark signal nonuniformity. Integration time is 10ms. Typical value is used for clock pulse and readout pulse. VOUT = 500mV. DR = VSAT/VDRK When optical integration time is shorter, the dynamic range sets wider because dark output voltage is in proportion to optical integration time. SE = VSAT/R1 Vos is defined as indicated below. D51 Vout D52 D53 D54 D55 S1 VOS GND -3- Clock Timing Diagram 5 ROG 0 5 SHUT 0 5 CLK D0 D1 D2 D3 D4 D21 D22 D23 D24 D53 D54 D55 S1 S2 S3 S4 VOUT Optical black (30 pixels) Dummy signal (55 pixels) Effective picture elements signal (3000 pixels) 1-Line output period (3066 pixels) 3100 or more clock pulses are required. ILX103A S2997 S2998 S2999 S3000 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 Dummy signal (10 pixels) -4- 0 -1 0 1 2 ILX103A Input Clock Voltage Condition Item VIH VIL Min. 3.0 0.0 Typ. VDD -- Max. 5.5 0.1 Unit V V This is applied to the all external pulses. (CLK, ROG, SHUT) CLK Timing (For all modes) t1 CLK t3 t2 t4 Item CLK pulse rise/fall time CLK pulse Duty1 1 100 x t4/ (t3 + t4) Symbol Min. 0 Typ. 10 50 Max. 100 60 Unit ns % t1, t2 -- 40 ROG, CLK Timing ROG t6 t7 t8 CLK t5 t9 Item ROG, CLK pulse timing 1 ROG, CLK pulse timing 2 ROG pulse rise/fall time ROG pulse period Note) is the period of CLK. -5- Symbol Min. 1/8 1/8 0 6 Typ. 1/4 1/4 10 10 Max. 3/8 3/8 100 20 Unit ns ns ns ns t5 t9 t6, t8 t7 ILX103A SHUT, CLK Timing SHUT t11 t12 t13 t15 CLK t14 Item SHUT pulse rise/fall time SHUT pulse period SHUT, CLK pulse timing 1 SHUT, CLK pulse timing 2 Symbol Min. 0 4000 150 150 Typ. 10 5000 200 200 Max. 100 -- 250 250 Unit ns ns ns ns t11, t13 t12 t14 t15 Note) The high periods of ROG and SHUT are separated for 10 or more. CLK Output Signal Timing 1 2 CLK t16 Vout Item CLK-Vout output delay time1 Symbol Min. -- Typ. 230 Max. -- Unit ns t16 1 fck = 500kHz, CLK Duty = 50%, CLK rise/fall time = 10ns 2 is data period. -6- ILX103A Application Circuit (Output gain low mode)1 SHUT ROG CLK SWG GND GND GND Vout Vgg VDD VDD 2 VDD NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0.01 22/10V 1/16V Signal output 3k 1000p 2SA1175 CLK ROG SHUT 1 This circuit diagram is the case when output circuit gain is low. 2 Connect T1 (Pin 13) to GND with 1000pF capacitor. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. -7- NC 5V T1 ILX103A Example of Representative Characteristics (VDD = 5V, Ta = 25C) Spectral sensitivity characteristics (Standard characteristics) 10 9 8 Relative sensitivity 7 6 5 4 3 2 1 0 400 500 600 700 Wavelength [nm] 800 900 1000 Output voltage vs. Temperature characteristics (Standard characteristics) 10 5 Output voltage rate 1 0.5 0.1 0.05 0.01 -10 0 10 20 30 40 50 60 Ta - Ambient temperature [C] -8- ILX103A Offset level vs. Temperature characteristics (Standard characteristics) 5 VOS - Offset level [V] 4 3 2 1 0 -10 VOS - Offset level [V] Vos ~ - -2.1mV/C Ta 5 Offset level vs. VDD characteristics (Standard characteristics) Ta = 25C 4 3 2 1 0 4.5 Vos ~ - 0.49 VDD 0 10 20 30 40 50 60 5 VDD [V] 5.5 Ta - Ambient temperature [C] Supply current vs. VDD characteristics (Standard characteristics) 14 IVDD - Supply current [mA] 12 10 8 6 4 2 0 4.5 5 VDD [V] 5.5 1 10 Ta = 25C Output voltage rate 5 10 Output voltage vs. Integration time (Standard characteristics) 50 - Integration time [ms] 100 -9- ILX103A Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-SIP Packages The following points should be observed when handling and installing cer-SIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.5mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm Upper ceramic layer 39N 29N 29N 0.9Nm Lower ceramic layer (1) Low-melting glass (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with a soldering iron. (3) Rapid cooling or heating. (4) Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. - 10 - ILX103A 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Normal output signal is not obtained immediately after device switch on. - 11 - Package Outline Unit: mm 16pin SIP 30.3 0.3 21.0 (7m x 3000Pixels) 2.4 3.2 0.5 4.65 0.8 2.23 0.3 1 16 4.0 5.0 0.2 0.25 1.325 0.3 0.3 M H No.1 Pixel - 12 - 5.08 0.4 Cer-SIP TIN PLATING 42 ALLOY 1.3g LS-D4(E) 1.27 1. The height from the bottom to the sensor surface is 1.6 0.3mm. 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5. PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS ILX103A DRAWING NUMBER 4.2 V |
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